1. Field of the Invention
The present invention relates to a PLL (Phase-Locked Loop) circuit to synchronize an internal clock with an external clock from another apparatus, more particularly, relates to a PLL circuit capable of synchronizing an internal clock with one of plural external clocks for an electronic automatic exchange and the like.
2. Description of the Related Art
A PLL circuit produces a clock synchronizing with a clock from an external apparatus and including no jitter. For example, the PLL circuit is installed in an electronic automatic exchange to produce a communication system clock which synchronizes with an AMI clock (hereinafter, called external 64k+8k clock) to be a synthetic clock of a clock of a 64 kHz frequency (hereinafter, called external 64k clock) and a clock of a 8 kHz frequency (hereinafter, called external 8k clock) transmitted from a network such as the INS network.
Further, there are many cases in that a PLL circuit is fabricated to be capable of receiving clocks from plural supply sources in consideration of troubles at a network to be an external clock supply source.
FIG. 7 illustrates a sample of an above described conventional PLL circuit. As shown in FIG. 7, the conventional PLL circuit is provided with receiver circuits (RCV) 31.sub.1 -31.sub.4, an input monitor circuit 33, an input selection circuit 34, a phase comparison circuit 35, a low-pass filter (LPF) 36, a voltage controlled oscillator (VCO) 37, a 8k clock producing circuit 38 and a clock driver (CLKDRV) 39.
The RCVs 31.sub.1 -31.sub.4 separate the 64k+8K clock into the external 64k clock and the external 8k clock. The RCVs 31.sub.1 -31.sub.4 receive the 64k+8K clocks (IN1-IN4) from various clock supply sources, respectively. The external 64k clocks separated in the RCVs 31.sub.1 -31.sub.4 are supplied to the input monitor circuit 33, and the external 8k clocks are supplied to the input selection circuit 34.
The input monitor circuit 33 outputs one input selection signal indicating an IN in a normal status among four input selection signals corresponding to the IN1 through the IN4. The external 64k clocks separated in the RCVs 31.sub.1 -31.sub.4 are used in the input monitor circuit 23 for determining which input selection signal is outputted. That is, the input monitor circuit 33 grasps the status of each IN by monitoring always the status of each external 64k clock (the presence of each signal), and outputs the input selection signal indicating one IN in the normal status. Moreover, in outputting the input selection signal indicating an IN, when it is detected that this IN becomes defective, the input monitor circuit 33 specifies one IN among the other INs in normal status and outputs the input selection signal indicating the specified IN into the input selection circuit 34.
The input selection circuit 34, what is called a 4-1 selector, outputs the external 8k clock from the RCV 31 corresponding to the IN indicated by the input selection signal from the input monitor circuit 33 to the phase comparison circuit 35.
The phase comparison circuit 35, in addition to this external 8k clock, receives a 8k clock for phase comparison to be a signal from the 8k clock producing circuit 38 (details is described later). The phase comparison circuit 35 outputs a pulse signal having a width and a polarity corresponding to the phase difference between these two clocks into the LPF 36.
The LPF 36 integrates the inputted pulse signal to thereby convert the pulse signal to a voltage signal including no high frequency component. Then, the LPF 36 supplies the voltage signal to the VCO 37 as a frequency control voltage.
The VCO 37 produces a clock of a frequency corresponding to the frequency control voltage, and produces the clock of the frequency of 16.384 MHz when the frequency control voltage of "2.5" V is supplied. The clock produced in the VCO 37 (hereinafter, called 16M clock or VCO clock) is supplied to the 8k clock producing circuit 38 and the CLKDRV 39.
The 8k clock producing circuit 38 produces a 8k clock by dividing the 16M clock produced in the VCO 37, and outputs it. The output from the 8k clock producing circuit 38 is inputted into the phase comparison circuit 35 and the CLKDRV 39.
The CLKDRV 39 supplies the 8k clock from the 8k clock producing circuit 38 and the 16M clock from the VCO 37 to a system (not shown) such as a communication system.
That is, the PLL circuit shown in FIG. 7 is fabricated to adjust the frequency of the VCO clock in a manner that the phase difference between the 8k clock outputted from the 8k clock producing circuit 38 and the external 8k clock supplied to the phase comparison circuit 35 becomes "0".
This PLL circuit produces an 8k clock including no jitter and coinciding with the external 8k clock concerning a phase and a frequency, therefore, a satisfied communication can be obtained. Moreover, when a trouble occurs in the IN including that external 8k clock, the IN is switched automatically and an 8k clock synchronized with the switched IN is produced, so that the communication can be continued.
In the conventional PLL circuit, however, there are some case that a trouble occurs in a system or a communication between systems when the IN is switched.
That is, when the external 8k clock inputted into the phase comparison circuit 35 is switched as the result which a trouble occurs in an IN, usually the phase of the external 8k clock before switching (i.e. the 8k clock for phase comparison outputted from the 8k clock producing circuit at that time) does not coincide with the phase of the external 8k clock after switching, therefore, the frequency of the VCO clock is adjusted in a manner that the phase difference between the 8k clock outputted from the 8k clock producing circuit 38 and the external 8k clock after switching becomes "0".
For instance, there may be a maximum phase difference of 62.5 .mu.s between the two external 8k clocks. Thus, in the worst case, immediately after changing over the clocks, there is the phase difference of 62.5 .mu.s between the external 8k clock and the 8k clock for phase comparison inputted into the phase comparison circuit 35. Assuming that the frequency variation range of the VC0 37 in the PLL circuit shown in FIG. 7 is .+-.50 ppm of the oscillating frequency, namely, about .+-.19 Hz, it takes a time to establish the synchronization after occurring this worst case, as described later.
In this case, since the phase comparison circuit 35 outputs the maximum (or minimum) frequency control voltage, the VCO 37 outputs the VCO clock of 16.384819 MHz which is the maximum oscillating frequency. The time for one clock of this VCO clock is "1/16.384819" MHz.sup.-1 =.+-.sec!, and the time for one clock of the VC0 clock at the central frequency is "1/16.384" .+-.sec!. Thus, the phase difference between the external 8k clock and the 8k clock for phase comparison becomes smaller 3.054586.times.10.sup.-12 sec! (1/16.384-1/16.384819 .+-.sec!) for one clock of the VCO clock. Therefore, it is necessary for the VC0 clock of at least 20461038 (=62.5.times.10.sup.-6 sec!/3.054586.times.10.sup.-12 sec!) until a synchronization is established. That is, it takes at least 1.24878 (=1/16.384819MHz!.times.20461038)sec! to establish the synchronization.
A PLL circuit is also known, in which the external 64k clock is inputted into the input selection circuit 33 and the external 8k clock is inputted into the input monitor circuit 23, namely, a PLL circuit which a synchronization is established with the 64k clock. When the 64k clock is used, the maximum phase difference becomes 7.8 .mu.sec. Thus, when such a PLL circuit is fabricated with the above VCO, it takes at least 0.15609 sec! to establish the synchronization in the worst case.
As above described, in the conventional PLL circuit, when the IN is switched, it takes a time corresponding to the phase difference between the external clocks before and after switching to establish the synchronization between the external clock and the clock for the phase comparison. Therefore, in the conventional PLL circuit, there are some cases that unstable clocks are supplied to a system for a relative long time during clock switching, as the result, there are some cases that a trouble occurs in a system or a communication between systems.